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Digital Still Camera LSIs
MN673282A
Image-Processing IC for Digital Still Cameras
s Overview
The MN673282A is an image-processing IC with JPEG function for digital still cameras. The MN673282A supports the analog video outputs provided by the RGB checker board pattern color filter CCD area image sensors such as the Panasonic MN39571 (which features an interlaced scanning technique and 2.31 million pixels) and MN39742 (which features an interlaced scanning technique and 1.33 million pixels).
s Features
* Supports both NTSC and PAL with a single 49.5 MHz oscillator. * Real-time monitoring with an image refresh rate of 30 Hz (25 Hz for PAL) * Integrates all functions from analog-to-digital signal input to JPEG input and output, and a monitor output, on a single chip. Supports JPEG compression and expansion. * Implements the highest image quality in its class with new Matsushita-developed image-processing technologies. * Maximum speed of under 1 second for all processing from full-resolution imaging through JPEG compression (Slightly over 800 ms, not including storing the data to the recording media.) * Fine mode function that reduces the amount of data to 1/4 that for full resolution. * Supports panorama mode with an aspect ratio of 1:3 (V:H) * Provides a teleconferencing mode that can extract and store an arbitrary VGA resolution subset of the full resolution image. * Thumbnail signal generation and processing function
s Applications
* Digital still cameras, cameras for use in FA and OA applications
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SW 1H FIFO 1H FIFO IPP (RGB) SW Encoder SW D/A 3 ch. 1H FIFO ROM ROM ROM YUV decoder 1H FIFO TV monitor or LCD(TFT) JPEG I/F SW SW JPEG CORE (DCT) (Quantization) (Hufman) MCC (ECC) (To the SW etc.) SW SW I/O Data 64 M-bit x 1 SDRAM SW CPU I/F Address SW SW I/O Address Data CPU Memory card
MN673282A
s Block Diagram
SW
OB clamp circuit
Data rate converter
ADout
in
Memory controller
SSG
Synchronization system signal output
Digital Still Camera LSIs
Vertical system CCD Transfer pulse Horizontal system CCD Transfer pulse
TG MN5286
Digital Still Camera LSIs
s Pin Arrangement
MN673282A
CPUWAIT VSS VDD CPUDT7 CPUDT6 CPUDT5 CPUDT4 CPUDT3 CPUDT2 CPUDT1 CPUDT0 TEST4 TESTO1 TESTO2 TESTO3 TESTO4 TESTO5 TESTO6 TESTO7 TESTO8 TESTO9 CCDSW FLTRSW1 FLTRSW0 TEST5 LCDCLK HDHEAD VDHEAD CBLK CSYNC HD VD VSS VDD BLIN BLKIN OSDIN OSDCLK EXTINT SWSUB MINTEST
123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83
CPURD CPUWR CPUCS CPUINT DEFAULT2 DEFAULT1 NRESET CPUAD0 CPUAD1 CPUAD2 CPUAD3 CPUAD4 CPUAD5 CPUAD6 CPUAD7 CPUAD8 CPUAD9 CPUAD10 CPUAD11 CPUAD12 CPUAD13 CPUAD14 CPUAD15 VDD VSS AVDD4 VREF AVSS4 GYC AVSS3 AVDD3 BNN AVSS2 AVDD2 RCN AVSS1 COMP IREF AVDD1 VSS VDD
124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42
TEST3 MCLK BA0 BA1 CKE DQM WE RAS CAS VSS VDD ADRS0 ADRS1 ADRS2 ADRS3 ADRS4 ADRS5 ADRS6 ADRS7 ADRS8 ADRS9 ADRS10 ADRS11 VSS VDD RAM0 RAM1 RAM2 RAM3 RAM4 RAM5 RAM6 RAM7 RAM8 RAM9 RAM10 RAM11 RAM12 RAM13 RAM14 RAM15
ADCLK FI FH2 CP1 CP2 DS1 DS2 PBLK HCLR SUB VDD VSS CH4 CH3 CH2 CH1 V4 V3 V2 V1 RWO RWI CDSIN9 CDSIN8 CDSIN7 CDSIN6 CDSIN5 CDSIN4 CDSIN3 CDSIN2 CDSIN1 CDSIN0 VDD VSS R H1 H2 TEST1 XI XO TEST2
(TOP VIEW)
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MN673282A
s Pin Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Pin Name ADCLK FI FH2 CP1 CP2 DS1 DS2 PBLK HCLR SUB VDD VSS CH4 CH3 CH2 CH1 V4 V3 V2 V1 RWO RWI CDSIN9 CDSIN8 CDSIN7 CDSIN6 CDSIN5 I/O O O O O O O O O O O I I O O O O O O O O O I I I I I I Test outputs Test inputs CDS data inputs Open Function A/D converter clock Field index Line index Optical black clamp Clamp pulse CDS pulse 1 CDS pulse 2 Pre-blanking pulse CCD horizontal transfer stop period
Digital Still Camera LSIs
Descriptions Clock used for the A/D converter. 24.75 MHz clock synchronized with HDHEAD (front side) Low for odd fields, high for even fields, and synchronized with interlaced scanning CCD. Outputs a low for the GR line signal and high for the BG line signal in the CDS data input. Clamps the optical black level of the CCD output input to the CDS chip. Output immediately after the stop of CCD horizontal transfer. This signal is normally not needed. Clamps the optical black level of the CCD output. Input to the CDS chip. Clamps the signal component of the CCD output and inputs that level to the CDS chip. Blanking signal used for preprocessing for the horizontal return period. Outputs a high level during the horizontal CCD transfer stop period.
Electronic shutter CCDSUB pulse Sweeps out unnecessary charge from the CCD substrate during electronic shutter operation. Digital system power supply (3.3 V) Digital system ground Test output DCLK (external TG interface) DATA (external TG interface) CS (external TG interface) Test outputs Open Mode setting clock output Mode setting data output Chip select Open
Connect to ground. CDS data input (MSB). CDS sampling is CDS data input (bit 9). applied to the CCD output and those levels CDS data input (bit 8). are A/D converted CDS data input (bit 7). with 10-bit resolution. CDS data input (bit 6).
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Digital Still Camera LSIs
s Pin Descriptions (continued)
Pin No. 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 Pin Name CDSIN4 CDSIN3 CDSIN2 CDSIN1 CDSIN0 VDD VSS R H1 H2 TEST1 XI XO TEST2 RAM15 RAM14 RAM13 RAM12 RAM11 RAM10 RAM9 RAM8 RAM7 RAM6 RAM5 RAM4 RAM3 RAM2 RAM1 RAM0 VDD VSS I/O I I I I I I I O O O I I O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I Digital system power supply (3.3 V) Digital system ground Test input Crystal oscillator element input and output Test input SDRAM data I/O Digital system power supply (3.3 V) Digital system ground Test output Test output Open Open Function CDS data inputs
MN673282A
Descriptions CDS data input (bit 5). CDS data input (bit 4). CDS data input (bit 3). CDS data input (bit 2). CDS data input (LSB). CDS sampling is applied to the CCD output and those levels are A/D converted with 10-bit resolution.
Must be held low during normal operation. Input Output Must be held low during normal operation. [MSB] Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 [LSB]
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MN673282A
s Pin Descriptions (continued)
Pin No. 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 Pin Name ADRS11 ADRS10 ADRS9 ADRS8 ADRS7 ADRS6 ADRS5 ADRS4 ADRS3 ADRS2 ADRS1 ADRS0 VDD VSS CAS RAS WE DQM CKE BA1 BA0 MCLK TEST3 VDD VSS AVDD1 IREF COMP AVSS1 RCN AVDD2 AVSS2 BNN AVDD3 AVSS3 I/O O O O O O O O O O O O O I I O O O O O O O O I I I I I I I O I I O I I Master clock output1 Test input Digital system power supply (3.3 V) Digital system ground Digital system power supply (3.3 V) Digital system ground SDRAM control outputs Function SDRAM address outputs [MSB] Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 [LSB]
Digital Still Camera LSIs
Descriptions
RAMCOL address-enable signal RAMROW address-enable signal RAM write-enable signal RAM data mask: for monitoring RAM clock enable RAM bank selection
Must be held low during normal operation.
Analog system power supply (3.3 V) If possible, a separate power supply system should be used. D/A converter control input D/A converter control input Analog system ground Analog signal output D/A converter current-reference input D/A converter comparator-voltage input If possible, a separate power supply system should be used. Outputs the R signal in RGB mode, the color difference signal (C) in component mode, and is unused in video output mode.
Analog system power supply (3.3 V) If possible, a separate power supply system should be used. Analog system ground Analog signal output If possible, a separate power supply system should be used. Outputs the B signal in RGB mode, the luminance signal (Y) in component mode, and the V signal in video mode.
Analog system power supply (3.3 V) If possible, a separate power supply system should be used. Analog system ground If possible, a separate power supply system should be used.
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Digital Still Camera LSIs
s Pin Descriptions (continued)
Pin No. 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 Pin Name GYC AVSS4 VREF AVDD4 VSS VDD CPUAD15 CPUAD14 CPUAD13 CPUAD12 CPUAD11 CPUAD10 CPUAD9 CPUAD8 CPUAD7 CPUAD6 CPUAD5 CPUAD4 CPUAD3 CPUAD2 CPUAD1 CPUAD0 NRESET DEFAULT1 DEFAULT2 CPUINT CPUCS CPUWR CPURD CPUWAIT VSS VDD CPUDT7 CPUDT6 CPUDT5 CPUDT4 I/O O I I I I I I I I I I I I I I I I I I I I I I I I O I I I O I I I/O I/O I/O I/O Digital system ground Digital system power supply (3.3 V) CPU interface CPU data bus (MSB) CPU data bus (bit 7) CPU data bus (bit 6) CPU data bus (bit 5) Hardware reset Default pin 1 Default pin 2 CPU interface Function Analog signal output Analog system ground D/A converter control input
MN673282A
Descriptions Outputs the G signal in RGB mode, the luminance signal (Y) in component mode, and the V signal in video mode. If possible, a separate power supply system should be used. D/A converter reference-voltage input
Analog system power supply (3.3 V) If possible, a separate power supply system should be used. Digital system ground Digital system power supply (3.3 V) CPU interface CPU address bus (MSB) CPU address bus (bit 15) CPU address bus (bit 14) CPU address bus (bit 13) CPU address bus (bit 12) CPU address bus (bit 11) CPU address bus (bit 10) CPU address bus (bit 9) CPU address bus (bit 8) CPU address bus (bit 7) CPU address bus (bit 6) CPU address bus (bit 5) CPU address bus (bit 4) CPU address bus (bit 3) CPU address bus (bit 2) CPU address bus (MSB) Low active input Must be held low during normal operation. Must be held low during normal operation. CPU interrupt signal output Chip select CPU data-bus write signal input CPU data-bus read signal input DRAM refresh flag
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MN673282A
s Pin Descriptions (continued)
Pin No. 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 Pin Name CPUDT3 CPUDT2 CPUDT1 CPUDT0 TEST4 TESTO1 TESTO2 TESTO3 TESTO4 TESTO5 TESTO6 TESTO7 TESTO8 TESTO9 CCDSW FLTRSW1 FLTRSW0 TEST5 LCDCLK HDHEAD VDHEAD CBLK CSYNC HD VD VSS VDD BLIN BLKIN OSDIN OSDCLK I/O I/O I/O I/O I/O I O O O O O O O O O I I I I O O O O O O O I I I I I O CCD switch Test input Test output Function CPU interface
Digital Still Camera LSIs
Descriptions CPU address bus (bit 4) CPU address bus (bit 3) CPU address bus (bit 2) CPU address bus (LSB) Must be held low during normal operation. Open
Must be held low during normal operation.
CCD color filter phase adjustment Must be held low during normal operation. switch Test input LCD clock Frame horizontal synchronizing signal Frame vertical synchronizing signal Composite blanking Must be held low during normal operation. Outputs the master clock (49.5 MHz) divided by 4. 12.375 MHz CCD (TG) horizontal synchronizing signal (This differs from a TV horizontal synchronizing signal.) CCD (TG) vertical synchronizing signal (This differs from a TV vertical synchronizing signal.) Composite (horizontal and vertical) blanking signal that conforms to the NTSC and PAL standards.
Composite synchronization signal Composite (horizontal and vertical) synchronization signal that conforms to the NTSC and PAL standards. Horizontal synchronizing signal (TV) Horizontal synchronizing signal that conforms to the NTSC and PAL standards.
Vertical synchronizing signal (TV) Vertical synchronizing signal that conforms to the NTSC and PAL standards. Digital system ground Digital system power supply (3.3 V) OSD interface Blue background-mode setting OSD blanking signal input OSD signal input Clock for the OSD IC Outputs the master clock (49.5 MHz) divided by 8.
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Digital Still Camera LSIs
s Pin Descriptions (continued)
Pin No. 162 163 164 Pin Name EXTINT SWSUB MINTEST I/O I O I Function External TG switching Drive mode discrimination pulse Test input
MN673282A
Descriptions Must be held high during normal operation. Unused. This pin should be left open. Must be held low during normal operation.
s Electrical Characteristics
1. Absolute Maximum Ratings Parameter Supply voltage(digital) Supply voltage(analog) Input pins voltage Output pins voltage Output current (2 mA pins) Output current (4 mA pins) Output current (16 mA pins) Power dissipation Operating temperature Storage temperature PD Topr Tstg Symbol DVDD AVDD VI VO IO Rating - 0.3 to +4.6 - 0.3 to +4.6 - 0.3 to VDD+0.3 - 0.3 to VDD+0.3 6 12 48 1 050 -20 to +70 -55 to +150 mW C C Unit V V V V mA
Note) 1. The absolute maximum ratings are limiting values under which the chip will not be destroyed. Operation is not guaranteed within these ranges. 2. All of the DVDD, AVDD, DVSS,and AVSS pins must be directly connected externally to the power supply or ground, respectively.
2. Operating Conditions at VSS = 0 V Parameter Supply voltage(digital) Supply voltage(analog) Ambient temperature Oscillator frequency Recommended external capacitor values
*
Symbol DVDD AVDD Ta fOSC CXI CXO
Conditions
Min 3.0 3.0 0
Typ 3.3 3.3 49.5 22 22
Max 3.6 3.6 70
Unit V V C MHz pF
Xtal = 49.5 MHz VDD = 3.3 V A feedback resistor is built in.
XI XO CXO

CXI
Note ) *: The oscillator characteristics depend on the type of the oscillator element used, external capacitors, and other factors. Consult the manufacturer of the oscillator element used to determine the oscillator circuit component values.
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MN673282A
s Electrical Characteristics (continued)
Digital Still Camera LSIs
3. DC Characteristics at DVDD = AVDD = 3.0 V to 3.6 V, DVSS = AVSS = 0 V, fOSC = 49.5 MHz, Ta = 0C to 70C Parameter Operating supply current Symbol IDD Conditions VI = VDD or VSS VDD = 3.3 V, with the output pins open. Min Typ 190 Max 285 Unit mA
Input pins 1: CMOS level pins RWI, BLIN, TEST1 to TEST5, BLKIN, CCDSW, CDSIN0 to CDSIN9, CPUAD0 to CPUAD15, CPUCS, CPURD, CPUWR, OSDIN, EXTINT, FLTRSW0, FLTRSW1, NRESET, DEFAULT1, DEFAULT2 High-level input voltage Low-level input voltage Input leakage current VIH VIL ILI VI = VDD or VSS VDD x 0.8 0 VDD VDD x 0.2 5 V V A
Input pins 2: CMOS level pins with pull-down resistor MINTEST High-level input voltage Low-level input voltage Pull-down resistor Input leakage current VIH VIL RIL ILIL VI = VDD VI = VSS VDD x 0.8 0 10 30 VDD VDD x 0.2 90 10 V V k A
Output pins 1: Push-pull outputs (2 mA pins) V1 to V4, BA0, BA1, CH1 to CH4, CP1, CP2, FH2, FI, WE, CAS, CKE, DQM, RAS, RWO, SUB, ADRS0 to ADRS11, CBLK, HCLR, PBLK, CSYNC, SWSUB, TESTO1 to TESTO9, CPUINT, HDHEAD High-level output voltage Low-level output voltage VOH VOL IOH = -2.0 mA VI = VDD or VSS IOL = +2.0 mA VI = VDD or VSS VDD - 0.6 0.4 V V
Output pins 2: Push-pull outputs (4 mA pins) DS1, DS2, HD, VD, MCLK, ADCLK, LCDCLK, OSDCLK, VDHEAD High-level output voltage Low-level output voltage VOH VOL IOH = -4.0 mA VI = VDD or VSS IOL = +4.0 mA VI = VDD or VSS VDD - 0.6 0.4 V V
Output pins 3: Push-pull outputs (16 mA pins) H1, H2, R High-level output voltage Low-level output voltage VOH VOL IOH = -16.0 mA VI = VDD or VSS IOL = +16.0 mA VI = VDD or VSS VDD - 0.6 0.4 V V
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Digital Still Camera LSIs
s Electrical Characteristics (continued)
MN673282A
3. DC Characteristics at DVDD = AVDD = 3.0 V to 3.6 V, DVSS = AVSS = 0 V, fOSC = 49.5 MHz, Ta = 0C to 70C (continued) Parameter Symbol Conditions Min Typ Max Unit Output pins 4: Three-state outputs (2 mA pins) CPUWAIT High-level output voltage Low-level output voltage Output leakage VOH VOL ILO IOH = -2.0 mA VI = VDD or VSS IOL = +2.0 mA VI = VDD or VSS VO = High-impedance state VI = VDD or VSS VO = VDD or VSS VDD - 0.6 0.4 5 V V A
I/O pins: CMOS level pins RAM0 to 15, CPUDT0 to CPUDT7 Low-level input voltage High-level input voltage High-level output voltage Low-level output voltage Output leakage VIH VIL VOH VOL ILO IOH = -4.0 mA VI = VDD or VSS IOL = +4.0 mA VI = VDD or VSS VO = High-impedance state VI = VDD or VSS VO = VDD or VSS VDD = 3.3 V, using an external crystal XI = VDD or VSS VDD = 3.3 V VDD = 3.3 V, XI = XO = VSS VDD = 3.3 V, XI = XO = VDD VDD x 0.8 0 VDD - 0.6 5 VDD VDD x 0.2 0.4 A V V V V
Oscillator pins XI, XO Standard oscillator frequency Internal feedback resistance High-level output current Low-level output current fOSC Rf IOH IOL 1.5 30 30 49.5 3.0 60 60 6.0 120 120 MHz k mA mA
4. AC Characteristics Parameter Input pin 1 XI Clock period Clock duty factor tcyc dclk See figure 1. See figure 1. 45 20.2 50 55 ns % Symbol Conditions Min Typ Max Unit
Input pins 2 CDSIN0 to CDSIN9, CPUAD0 to CPUAD15, CPUCS, CPURD, CPUWR, NRESET Input setup time Input hold time tsu thd See figure 1. See figure 1. 5 10 ns ns
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MN673282A
s Electrical Characteristics (continued)
3. AC Characteristics (continued) Parameter Symbol Conditions
Digital Still Camera LSIs
Min
Typ
Max
Unit
Output pins BA0, BA1, CH1 to CH3, CP1, FH2, FI, CAS, RAS, DS1, DS2, CBLK, HCLR, PBLK, CSYNC, CPUINT, HDHEAD, VDHEAD, HD, VD, ADRS0 to ADRS11, WE, CKE, CPUWAIT Output delay time tod With a 70 pF load, and a 50% output level. See figure 1. 32 ns
Input/Output pins RAM0 to RAM15, CPUDT0 to CPUDT7 Input setup time Input hold time Output delay time tsu thd tod See figure 1. See figure 1. With a 70 pF load, and a 50% output level. See figure 1. 5 10 32 ns ns ns
tcyc thi Clock XI dclk = thi/tcyc VDD /2
tsu Input
thd VDD /2
tod Output VDD /2
Figure 1. I/O Timing
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Digital Still Camera LSIs
s Electrical Characteristics (continued)
5. D/A Converter at DVDD = AVDD = 3.3 V, DVSS = AVSS = 0 V, Ta = 0C to 70C Parameter Symbol Conditions Min Typ
MN673282A
Max
Unit
Recommended D/A Converter Operating Conditions Analog input pins: IREF, VREF, COMP Analog output pins: RCN, BNN, GYC Reference voltage VREF Inserted between the COMP and AVDD pins. Inserted between the analog output and VSS pins. Inserted between the IREF and VSS pins. RL RIREF 4.5 0.6 1.235 1.0 200 31.6 V F k
External phase compensation capacitor CCOMP External output resistor External-bias current setting resistor D/A converter characteristics Resolution Linearity error Differential linearity error Full-scale output current Full-scale output voltage setting range * RES INLE DNLE IFS VO
fclk = 20.0 MHz, VDD = 3.3 V, RL = 200 , RIREF = 31.6 k, VREF = 1.235 V
1.5 1.0 5.0
10 2.5 2.0 5.5 1.1
bit LSB LSB mA V
Note) * : This is the range over which output as a D/A converter is possible. Note that INLE, DNLE, and other characteristics are not guaranteed over this range.
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MN673282A
s Application Circuit Example
* Interlaced 2.31 megapixel CCD camera system structure
Digital Still Camera LSIs
MN39571 CCD
AN2104 CDS * A/D TV MN673282A
MN5286 Vertical driver x2 MN31121SA x 2 Smart Media Compact Flash TG
or
LCD
Microcontroller MN10xC Series device
SDRAM 64 M-bit (16 -bit)
* Interlaced 1.33 megapixel CCD camera system structure
MN39742 CCD
AN2104 CDS * A/D TV MN673282A
MN5281 Vertical driver x2 MN31121SA x 2 Smart Media Compact Flash TG
or
LCD
Microcontroller MN10xC Series device
SDRAM 64 M-bit (16 -bit)
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Digital Still Camera LSIs
s Package Dimensions (Unit: mm)
* LQFP164-P-1818
MN673282A
20.00.2 18.00.1 123 124 83 82 (1.0) 18.00.1 164 1 (1.0) 0.4 0.16 41
+0.10 -0.05
42
20.00.2
0.1 M 1.40.1 1.7max.
0.15 -0.05
+0.10
(1.0)
0.10.1
0.1
Seating plane
0 to 10 0.50.1
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Request for your special attention and precautions in using the technical information and semiconductors described in this material
(1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuit examples of the products. It does not constitute the warranting of industrial property, the granting of relative rights, or the granting of any license. (3) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: * Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. * Any applications other than the standard applications intended. (4) The products and product specifications described in this material are subject to change without notice for reasons of modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, redundant design is recommended, so that such equipment may not violate relevant laws or regulations because of the function of our products. (6) When using products for which dry packing is required, observe the conditions (including shelf life and after-unpacking standby time) agreed upon when specification sheets are individually exchanged. (7) No part of this material may be reprinted or reproduced by any means without written permission from our company.
Please read the following notes before using the datasheets
A. These materials are intended as a reference to assist customers with the selection of Panasonic semiconductor products best suited to their applications. Due to modification or other reasons, any information contained in this material, such as available product types, technical data, and so on, is subject to change without notice. Customers are advised to contact our semiconductor sales office and obtain the latest information before starting precise technical research and/or purchasing activities. B. Panasonic is endeavoring to continually improve the quality and reliability of these materials but there is always the possibility that further rectifications will be required in the future. Therefore, Panasonic will not assume any liability for any damages arising from any errors etc. that may appear in this material. C. These materials are solely intended for a customer's individual use. Therefore, without the prior written approval of Panasonic, any other use such as reproducing, selling, or distributing this material to a third party, via the Internet or in any other way, is prohibited.
2001 MAR

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